(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to obtain global planarization for semiconductor chips comprised of DRAM cells, with crown capacitor structures, and also comprised of devices in peripheral regions, exhibiting less severe topography than encountered in the DRAM cell.
(2) Description of Prior Art
Crown shaped capacitor structures, comprised with various configurations of vertical features, have allowed the capacitance of dynamic random access memory, (DRAM), devices, to be increased without increasing the horizontal dimension of the DRAM device. This attractive approach, allowing increases in DRAM device densities to be realized, can however present difficulties when subsequent metal wiring procedures are performed. The large difference in height between the DRAM cell, comprised with the severe crown shaped topography, and the flatter peripheral region, comprised of conventional transfer gate transistors, can result in electrical opens or shorts, when metal interconnect structures traverse the severe topography created with the use of DRAM, crown shaped capacitor structures.
This invention will describe a fabrication process sequence for global planarization of the inter-level dielectric, (ILD), layers that overlay both the crown shaped, DRAM devices, as well as peripheral, or non-DRAM, logic device regions. The process features the use of a thin silicon nitride shape, used to protect peripheral region, ILD layers, from insulator removal procedures, used to expose the vertical features of the DRAM crown shaped capacitor structure. Prior art, such as Auer et al, in U.S. Pat. No. 5,623,164, as well as Koh et al, in U.S. Pat. No. 5,674,773, describe methods such as chemical mechanical polishing, and reflowable ILD layers, to achieve global planarization, however these prior arts do not use the novel silicon shape, described in this invention, to preserve the ILD layers, residing in non-DRAM regions, thus allowing global planarization to be realized.